Before describing the present invention, a conventional semiconductor test apparatus is explained with reference to FIG. 4 to make it easier to understand the present invention.
As shown in FIG. 4, a semiconductor test apparatus 100 generally comprises a period generator 400, a pattern generator 300, a timing generator 200, a waveform formatter 500 and a logical comparison circuit 600.
The period generator 400 outputs period data on the basis of an input reference clock. The period data is sent to the pattern generator 300 and also sent to the timing generator 200 as a Rate signal (see FIG. 6). The period generator 400 generates an address for saving data in memories 211-2, 211-3 described later (see FIGS. 5, 8).
The pattern generator 300 outputs a test pattern signal and an expected pattern signal on the basis of the period data. The test pattern signal is sent to the timing generator 200, and the expected pattern signal is sent to the logical comparison circuit 600.
The reference clock signal, the test pattern signal and the period data signal (Rate signal) are input to the timing generator 200, and the timing generator outputs a formatted clock signal and a comparative clock signal. The formatted clock signal is sent to the waveform formatter 500, and the comparative clock signal is sent to the logical comparison circuit 600.
The waveform formatter 500 formats the formatted clock signal into a waveform necessary for a test, and then sends a formatted pattern signal to a semiconductor device under test (hereinafter also abbreviated as “DUT” (device under test)) 700.
The logical comparison circuit 600 compares a response output of the DUT 700 with the expected pattern signal on the basis of the comparative clock signal. Thus, whether the DUT 700 is good or bad is judged depending on whether the response output corresponds to the expected pattern signal.
Next, the basic configuration of the timing generator is explained with reference to FIG. 5.
FIG. 5 is a schematic configuration diagram showing a configuration example of the timing generator commonly used today.
As shown in FIG. 5, a timing generator 200a comprises a plurality of timing generating sections 210-1 to 210-n for outputting a signal (TG OUT) to which a predetermined delay amount has been added, and a clock distribution circuit 220a which distributes a clock to these timing generating sections 210-1 to 210-n.
As shown in the drawing, each of the timing generating sections 210-1 to 210-n includes a logical variable delay circuit 211 which generates and outputs a signal indicating a delay time on the basis of a reference signal Refclk, and an analog variable delay circuit 212 which provides a delay amount to a data signal on the basis of the signal from this logical variable delay circuit 211.
The logical variable delay circuit 211 includes a counter 211-1, first storage means (Memory(U)) 211-2, second storage means (Memory(L)) 211-3, calibration data storage means (CAL Data) 211-4, a correspondence detection circuit 211-5, an adder 211-6 and clock period delay means 211-7.
As shown in FIG. 5, the analog variable delay circuit 212 includes an AND circuit 212-1, a first variable delay circuit 212-2, and a second variable delay circuit 212-3.
Next, an operation of the timing generator will be described with reference to FIG. 6.
FIG. 6 is a timing chart showing a change of each signal with time in each constituting section of the timing generator.
As shown in the drawing, it is assumed that a reference clock (Refclk) signal having a period of 10 ns is input to the timing generator 200a (FIG. 6(a)).
Then, an output timing (test cycle TC) of a signal (TG Out, a delay clock in the semiconductor test apparatus 100) output from the timing generator 200a includes a point (TC1) 5 ns from a first start, and a point (TC2) 12 ns from a second start (after one period of the Refclk signal from the first start) (FIG. 6(b)).
A Rate signal indicating a start point is input to the timing generator 200a (FIG. 6(c)). In response to the input of the Rate signal, the counter 211-1 is cleared to 0 (FIG. 6(d)). Then, when the Rate signal is not input, the counter 211-1 is incremented one by one at each period of the Refclk signal (FIG. 6(d)).
The first storage means 211-2 stores a quotient when the test cycle (TC) of the output signal (TG Out) is divided by the period of the Refclk signal.
Furthermore, the second storage means 211-3 stores a remainder when the test cycle (TC) of the output signal (TG Out) is divided by the period of the Refclk signal.
For example, with regard to 5 ns which is the test cycle of the first output signal, the quotient and remainder are calculated using the following equation:5÷10=0 . . . 5  (Equation 1)
A quotient of 0 and a remainder of 5 ns are calculated by Equation 1. The quotient “0” is stored in the first storage means 211-2, and the remainder “5 ns” is stored in the second storage means 211-3 (FIG. 6(e), (f)).
Moreover, with regard to, for example, 12 ns which is the test cycle of the second output signal, the quotient and remainder are calculated using the following equation:12÷10=1 . . . 2  (Equation 2)
A quotient of 1 and a remainder of 2 ns are calculated by Equation 2. The quotient “1” is stored in the first storage means 211-2, and the remainder “2 ns” is stored in the second storage means 211-3 (FIG. 6(e), (f)).
Furthermore, the correspondence detection circuit 211-5 detects the correspondence (match) between a counted value of the counter 211-1 and data stored in the first storage means 211-2. The correspondence detection circuit outputs a detection signal when the two correspond to each other, but outputs no detection signal when the two do not correspond to each other.
For example, at the first cycle of the Refclk signal, the counted value corresponds to the stored data because the counter indicates “0” and the memory indicates “0”. In this case, a detection signal is output (FIG. 6(g)).
Furthermore, for example, at the second cycle of the Refclk signal, the counted value does not correspond to the stored data because the counter indicates “0” and the memory indicates “1”. In this case, no detection signal is output (FIG. 6(g)).
Then, for example, at the third cycle of the Refclk signal, the counted value corresponds to the stored data because the counter indicates “1” and the memory indicates “1”. In this case, a detection signal is output (FIG. 6(g)).
The adder 211-6 adds up the remainder stored in the second storage means 211-3 and CAL Data stored in the calibration data storage means 211-4 to send the result to the clock period delay means 211-7.
In response to the detection signal from the correspondence detection circuit 211-5 and an addition result (Carry) from the adder 211-6, the clock period delay means 211-7 sends, to the variable delay circuit 212, a delay amount signal (coarse resolution delay amount signal) whose resolution is equal to one cycle of the Refclk signal.
This clock period delay means 211-7 is specifically a combination of a shift register and a selector, and shifts such a position to select the timing of the Refclk signal, to generate the delay with the resolution of the period of the Refclk signal.
Upon receiving the delay amount signal from the clock period delay means 211-7 of the logical variable delay circuit 211 and the clock from the clock distribution circuit 220a, the AND circuit 212-1 of the analog variable delay circuit 212 outputs the delay amount signal.
The first variable delay circuit (Coarse Delay) 212-2 delays the data signal with a coarse resolution.
The second variable delay circuit (Fine Delay) 212-3 delays the data signal with a fine resolution. This delayed data signal is output as TG OUT.
According to such a configuration, the timing generator 200a can generate a desired delay time in an analog manner to output a delay clock.
However, in recent years, with miniaturization of a semiconductor device, a scale of a circuit to be mounted on one chip of an LSI increases, and it increasingly becomes difficult to distribute the clock and the data.
This also applies to design of the timing generator. It is demanded in distributing the clock that a propagation delay time be short, a skew between the timing generating sections be minimized, power consumption be small and noises generated by the circuit itself be low, but in reality, trade-off of these conditions must be made to realize the distribution of the clock and the data (e.g., see Japanese Patent Publication Laid-open No. 2001-235521 and Japanese Patent Publication Laid-open No. 8-94725).
For example, the conventional clock distribution method shown in FIG. 5 is designed so that an equal load capacity is obtained with buffers having the same driving capability. In this technique, the buffers have the same driving capability and the equal load capacity, so that a peak of a consumed current is distributed in a time direction, and a current waveform is a rectangular wave as shown in FIG. 7. As shown by this rectangular wave, the peak of the consumed current is distributed in the time direction, and hence the noises are reduced.
Moreover, in addition to the clock distribution technique shown in FIG. 5, a clock distribution technique shown in FIG. 8 is also known. This technique is similar to a clock distribution structure referred to as an “H-Tree structure”, which increases distribution stages in a reverse tournament system. In this distribution technique, fan-out, wiring lines and the like of a distribution destination are set to the same conditions, and a wiring line delay and a load capacity are set to be equal, whereby a difference of a delay time between distribution paths can be set to be equal.
Patent document 1: Japanese Patent Publication Laid-open No. 2001-235521
Patent document 2: Japanese Patent Publication Laid-open No. 8-94725